The present embodiments relate to memory control in digital computing systems, and are more particularly directed to circuits, systems, and methods in these environments for more efficiently controlling precharging of memory banks.
Memory control is typically accomplished in the computing art by a mechanism referred to as a memory controller, or often as a DRAM controller since dynamic random access memory ("DRAM") is often the type of memory being controlled. A DRAM controller may be a separate circuit or a module included within a larger circuit, and typically receives requests for accessing one or more memory locations in the corresponding memory. To respond to each request, the memory controller implements sufficient circuitry (e.g., address decoders and logic decoders) to provide the appropriate control signals to a memory so that the memory is properly controlled to enable and disable its storage circuits.
While some DRAM controllers are directed to certain improvements in memory access efficiency, it has been observed in connection with the present inventive embodiments that some limitations arise under current technology. These limitations are caused by DRAM controllers when activating or de-activating memory rows. To better illustrate these operations and the corresponding drawbacks, FIG. 1a illustrates a block diagram of a portion of a prior art computing system 10. System 10 includes a memory controller 12 which receives a REQUEST from an addressing component (not shown) either within or having access to system 10. In response to the REQUEST, memory controller 12 controls a DRAM 14 so that data is either read from, or written to, DRAM 14 in an orderly fashion. More particularly, this control is accomplished via a control bus 16, which typically includes the following six signals and corresponding conductors, where a more detailed discussion of the function of these signals is presented later: (1) an address signal ADDR on a multiple conductor line 18, where the number of conductors is selected according to the number of address bits to be communicated to DRAM 14; (2) a row address strobe signal RAS* on a conductor 20, where the superscript asterisk indicates that the signal is an active low signal (and where this same convention is used for other signals hereafter used in this document); (3) a column address strobe signal CAS* on a conductor 22; (4) an output enable signal OE* on a conductor 24; (5) a read/write R/W* signal on a conductor 26, and a DATA signal on a multiple line conductor 28, where the number of conductors is selected according to the number of data bits to be communicated to or from DRAM 14. Lastly, note that bus 16 may include still additional signals not shown in FIG. 1a but known in the art, such as a chip enable signal and a CKE signal. These and other signals, however, are not detailed here so as to simplify and focus the following discussion.
The operation of the above-introduced conductors may be appreciated further from the timing diagram of FIG. 1b, which depicts the control signals communicated from memory controller 12 to DRAM 14 to accomplish a single access of DRAM 14 along with the output of DATA from DRAM 14 in response to the control signals. For the present example, this single access is a read operation with it understood that a write operation is similar in various timing respects and in any event will be appreciated by one skilled in the art. First, before time t0, the output enable signal OE* is asserted and, as a result, the data output of DRAM 14 is permitted to occur, that is, the output is not placed in a high impedance state which is what occurs when the output enable signal OE* is de-asserted. Next, at time t0, the R/W* is asserted low, thereby indicating that the next access to occur is a read. Next, at t1, the row address for the desired read of DRAM 14 is asserted on address conductors 18. Next, at t2, RAS* is asserted low, thereby indicating that the row address on address conductors 18 is valid and, thus, thereby causing that row address to be accepted by DRAM 14 for decoding and activation of the appropriate row in DRAM 14. Next, at t3, the column address for the desired read of DRAM 14 is asserted on address conductors 18. In this regard, note therefore that address conductors 18 may carry either a row or column address and, thus, it is the assertion of either RAS* or CAS* that determines the interpretation of which type of address is being communicated. Thus, at t4, CAS* is asserted low, thereby indicating that the column address on address conductors 18 is valid and, thus, thereby providing a column address which, when decoded by DRAM 14, causes one or more columns of the activated row to be selected. In response, the data for the selected column(s) is output from the data array of DRAM 14 and coupled to multiple line conductor 28, thereby providing the DATA signal so the data is available for any circuit having access to that conductor.
The preceding illustration and example, while relatively straightforward and well known in the art, provide a background to further introduce drawbacks which arise from the current state of the art as memory systems become more complex than that shown in FIG. 1. More particularly, the above process typically repeats for each access of a row in DRAM 14. Further in this regard, FIG. 1b illustrates a time t5 at which RAS* is de-asserted. In response, the row which is currently active is de-activated, typically by pre-charging the bit lines which allow access to that row. In this regard and importantly, note that a sufficient amount of time must pass for this precharging operation to reach a satisfactory state of equilibrium, that is, to fully precharge the cell before it may be accessed another time. Thus, for each operation of a row access, there is not only the time to access the row in response to the assertion of RAS* and CAS*, but there is also the time to conclude the access and then prepare for the next access by de-asserting RAS* (i.e., precharging the cell) for a sufficient period of time. Stated in an alternative manner, before a next row may be accessed, the previous row must be de-activated (e.g., precharged), and in the prior art that is commonly achieved by the RAS* signal, either alone or in combination with yet additional signals. Thus, in a worst case scenario, both of these times aggregate to impose overhead on DRAM 14, that is, time in which no data is communicated on conductor 28. Additionally, and as improved upon by the inventive embodiments described later, note that this type of precharge operation requires that at least conductor 20 of bus 16 become available before a row may be de-activated, and often this event does not occur until some delay in time due to its relation to other signals of bus 16.
The above conditions may be further complicated where, as is becoming more frequent in contemporary systems, DRAM 14 is a multiple bank memory. For example, DRAM 14 may include two, four, or some other number of banks in excess of one bank, where each bank may be accessed independently of the other. Such multiple bank systems sometimes are implemented in a manner which permits some type of concurrency, meaning an operation may be taken with respect to one of the banks while a different operation is taken with respect to a different one of the banks. Accordingly, this concurrency may reduce overall overhead as compared to a system with a single bank having a storage capacity equal to the total storage capacity of the multiple bank system Nevertheless, the addressing scheme of FIGS. 1a and 1b, or a variant thereof, usually is imposed in such a system. Once again, therefore, there are constraints due to the time required by both activating and precharging a row in one bank before then activating the next row in the same bank. In addition, note that it is contemplated in some multiple bank systems to leave a row in a given bank active for as long as possible, where there is hope or expectation that multiple addresses to the given bank will be to the same row. In this manner, since the row is left active, the data may be communicated with respect to the row without interjecting precharge sequences of that row between each successive access. However, the present inventor recognizes that even in such approaches at some point it is still required that the row will no longer be active, such as when an address is received to the same bank and is directed to a different row. At this point, therefore, once again the type of scheme depicted by FIG. 1a will cause overhead delay due to the precharging of one row and the activation of another row through the operation of the RAS* and possibly related signals.
In view of the above, there arises a need to address the drawbacks of the prior art and provide improved memory control for reducing memory access latency.